John D. Lynch
Director, Computer Engineering & Design Education Program
Department
of Science & Engineering
Oregon
Health & Science University
20000
NW Walker Road
Beaverton,
Oregon 97006
jdlynch@csee.ogi.edu
Tel. 503-748-7305
Office: Jack
Murdock Building 539
Teaching
OHSU
Courses
EE570/670
Advanced Logic Design (Fall)
EE571/671
System-on-Chip Design with Programmable Logic (Winter)
EE572/672
Advanced Digital Design: Timing and Test (Spring)
EE573/673
Computer Organization and Design (Fall)
EE577/677
Applied Hardware Verification (Summer)
Invited
Short
Courses
Digital
System Timing: 2-day short course at Halmstad University,
Halmstad, Sweden, June 2003
Timing-Driven
Verilog Synthesis for High-Performance System-on-Chip Design:
4-day short course at
Shanghai
Research
Center for Integrated Circuit Design, Shanghai, China, August 2004
Awards
Intel
Curriculum Development Fellowship Award recipient 2005
Research Interests
-
System-on-chip
design and verification for FPGAs and ASICs
-
Asynchronous
logic circuits and systems
-
Fault-tolerant
logic design
-
Hardware
description and verification languages
Background
I joined the OSHU faculty in 2002 after 23-year
career in industry working in the field of digital system
design.
My work from 1990 to 2002 focused on synthesis and timing analysis of ASICs and
FPGAs.
1998 -
2002 Pixelworks,
Inc., Director, IC Design Engineering
1995 -
1998 InFocus
Corporation, Manager, ASIC Design Engineering
1992 -
1995 Adaptive Solutions, Inc.
1990 -
1992 Pyramid Technology Corporation
(now part of Fujitsu Siemens Computers)
1988 -
1990 Advanced
Micro Devices
1982 -
1988 FPS Computing (now part of Sun
Microsystems)
1979 -
1982 Rockwell International, Space
Systems Division (now part of The Boeing
Company)
1979
BS Electrical Engineering, Cum Laude, University
of Utah
Publications
J. Lynch, “Teaching Digital System Timing: A
Comprehensive Approach”, IEEE Transactions on Education, Vol. 51, Issue
2, August 2008
J.
Lynch, "A Novel Graduate Course Takes a Systematic Approach to Teaching
Digital System Timing", Proceedings
of the 2007 IEEE International Conference on Microelectronic Systems Education
J.
Lynch, D. Hammerstrom and R. Kravitz, "A
Coherent FPGA-Based System-on-Chip Design Curriculum", Proceedings
of the 2005 IEEE International Conference on Microelectronic Systems Education
J.
Lynch and H. Schiefer, “Concurrent Engineering Delivers at the Chip and System
Level,” Integrated System Design,
December 1997
R.
Fazzari and J. Lynch, “The Second Generation FPS T Series: An Enhanced Parallel
Supercomputer”, Proceedings of the
Third Conference on Hypercube Concurrent Computers and Applications
- Volume 2, 1988
Patents
U.S.
Patent No. 5,787,095: Multiprocessor
computer backplane bus.
U.S.
Patent No. 5,581,713: Multiprocessor
computer backplane bus in which bus transactions are classified into different
classes for arbitration.
Last
updated 2 July 2008